The minimum feature sizes of integrated circuits (ICs) have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography.
In semiconductor technologies, a plurality of photomasks or masks are formed with predesigned integrated circuit (IC) patterns. The plurality of masks are used to transfer those predesigned IC patterns to multiple semiconductor wafers in lithography processes. The predesigned IC patterns formed on the masks are master patterns. Any defect on a photomask will be transferred to multiple semiconductor wafers and cause yield issues. Therefore, the fabrication of a mask utilizes a high precision process. Further inspection and follow-up repair are also implemented to ensure that each mask is fabricated with high quality. However, existing practices on inspection and repairing of a mask are time-consuming and costly.
Known methods use an optical mask microscope to emulate the wafer image to inspect defects on the mask and predict the wafer image. Emulated images obtained by an optical microscope are not very similar to the image obtained by a scanner or stepper, and are different from the actual photoresist image due to refraction and reflection in the film stacks of the wafer. In addition, current empirical models lump optical and chemical effects. Thus, current methods do not accurately predict the optical behavior in the photoresist. Accordingly, what is needed is a method and system that addresses the above stated issues.